Dealing with design complexity

Featuring a scalable VLIW/SIMD architecture, up to 128-bit SIMD, a variable length pipeline and support for both fixed and floating point operations, The CEVA-X delivers 2x more DSP horsepower while consuming 50% less power than the previous generation CEVA-X. The architecture also includes a dedicated 32-bit zero latency Instruction Set Architecture (ISA), 32-bit hardware division and multiplication, dynamic branch prediction and ultra-fast context switching for the efficient control processing required in modern baseband designs.

The CEVA-X4 is the first core based on the new CEVA-X architecture, targeting the most complex workloads of multi-RAT, multi-carrier, PHY control processing in 2G/3G/4G/5G basebands.

Mike Demler, Senior Analyst, The Linley Group, commented: “As the industry adopts LTE Advanced Pro and the promise of 1Gbps cellular download speeds, existing modem architectures will require a comprehensive overhaul to meet the increasingly stringent performance and power constraints. CEVA is addressing this need with a new baseband processor architecture, which effectively combines its high performance DSPs with real time control capabilities to handle the complete baseband system. Furthermore, with advanced features such as the capacity to process up to five carrier components in parallel, the CEVA-X4 provides its customers with a roadmap towards 5G.”

The CEVA-X4 was specifically designed to solve the three most critical challenges in next generation modem designs:

• Efficient control processing: For multi-carrier aggregation there is a significant increase in L1 PHY control processing. For example, next generation Rel-13 LTE Advanced Pro modems are required to deal with up to five carrier components in parallel and handle multiple PHY control tasks on multiple carriers, in tandem.

• Powerful DSP processing: A considerable boost in DSP performance is required to support a heavy LTE workload including per-channel measurement, calibration and decoding as well as legacy RAT.

• Advanced system control: Complex system scheduling and data traffic management is essential to deal with the many accelerators, DSPs and coprocessors in the system, within a low latency constraint.

To overcome these challenges, the CEVA-X4 incorporates a set of baseband optimised features and functions in an efficient manner. This 128-bit wide VLIW/SIMD processor features eight MAC units in four identical Scalar Processing Units (SPUs) and a ten-stage pipeline, capable of running at 1.5GHz in 16nm and achieving 16 Giga Operations Per Second (GOPS). The processor’s efficient control features include an integer pipeline, a complete 32-bit RISC ISA including hardware division and multiplication, and a Branch Target Buffer (BTB), achieving a CoreMark/MHz score of 4.0.

For system control, the CEVA-X4 brings a holistic approach to modem design, utilising the CEVA-Connect technology to orchestrate the entire PHY system, comprising of DSPs, coprocessors, accelerators, memories and system interfaces. It is equipped with dedicated hardware coprocessor interfaces and an automated data and control traffic management mechanism that eliminates any software intervention. Its memory subsystem supports an advanced non-blocking 2-way or 4-way caches with hardware and software pre-fetch capabilities.

Michael Boukaya, Vice President and General Manager, Wireless Business Unit at CEVA, commented: “The enormous complexity involved with building a modern baseband requires a new approach to solving the mounting design bottlenecks. The CEVA-X4 offers licensees the capability to develop a vastly simplified multi-mode modem system architecture with a perfect balance of DSP and control processing. Its monumental improvements over previous generation PHY control DSPs are indicative of the deep baseband expertise we accumulated over two decades in that industry, and ensure that the CEVA-X4 exceeds the most demanding requirements for next-generation 4G and 5G standards.”