Cadence tapes out 16G UCIe advanced package IP on TSMC’s N3E process technology

Implemented on TSMC’s 3DFabric CoWoS-S silicon interposer technology, the IP offers high bandwidth density, efficient low-power performance, and superior low latency, making it ideal for applications requiring extreme compute power. Cadence UCIe IP provides an open standard for chiplet die-to-die communication, which is becoming more critical as artificial intelligence/machine learning (AI/ML), mobile, automotive, storage, and networking applications are driving the need to move from monolithic integration to system-in-package (SiP) chiplets.

Cadence is currently engaged with a pipeline of Tier 1 customers, and UCIe advanced package IP collateral from the N3E test chip tapeout is shipping and available. The pre-verified solution can save customers time and effort through rapid integration.

The heterogeneous integration of Cadence’s UCIe PHY and controller eases chiplet solutions with die reusability. The complete solution includes the following, which can be delivered with a complement of Cadence Verification IP (VIP) and TLM models:

UCIe Advanced Package PHY: Designed for a bump pitch that enables greater than 5Tbps/mm of die edge bandwidth density, the UCIe advanced package PHY offers options that allow greater throughput performance while significantly improving power efficiency. It is flexible for integration on multiple types of 2.5D advanced packages, such as silicon interposer, silicon bridge, RDL, and fanout-based packaging.

UCIe Standard-Package PHY: Options allow customers to reduce costs while maintaining high bandwidth and power efficiency. Cadence’s circuit design allows customers to design down to the lower limits of the standard’s bump pitch range to allow maximum BW/mm while also enabling longer reach.

UCIe Controller: A soft IP that can be synthesised for multiple technology nodes, the UCIe controller is offered in a variety of options for different target applications and enables streaming, PCI Express (PCIe), and CXL protocols.

“The UCIe Consortium supports companies designing chiplets for use in standard and advanced packaging. We are thrilled to extend our congratulations to Cadence on reaching the tapeout milestone for the advanced package test chip which uses the die-to-die interconnect based on the UCIe 1.0 specification,” said Dr. Debendra Das Sharma, Chairman at the UCIe Consortium. “Member company advancements in IP (scaling) and VIP (testing) are important components in the ecosystem. When paired with participation in UCIe work groups the industry will continue to see new chiplet based designs entering the market that are based on open industry standards that foster interoperability, compatibility, and innovation.”

“Cadence has been an industry pioneer in chiplet system solution offerings and continues to push the envelope of performance and power efficiency for a wide range of multi-chiplet applications in advanced nodes and packaging architectures,” said Sanjive Agarwala, Corporate Vice President and General Manager of the IP Group at Cadence. “We see great value in aligning interconnect standards across the industry, and UCIe IP serves as a bridge, enabling open chiplet solutions for large SoCs reaching or exceeding the maximum reticle limit for manufacturing. The recent UCIe advanced package tapeout on the TSMC N3E process is a key milestone and commitment toward enabling customers with an open chiplet connectivity standard.”

The Cadence 16G UCIe 2.5D advanced package IP supports Cadence’s Intelligent System Design strategy, which enables SoC design excellence.