AMD sets STAC benchmark electronic trade execution world record

This results in up to a 49% tick-to-trade latency reduction compared to the previous record and is the fastest published STAC-T0 benchmark result to date. The previous highest speed, up to 24.2ns, also came from reference design utilising AMD accelerators.

STAC benchmarks are the industry standard for testing solutions that enable high-speed analytics on time-series tick data. The STAC-T0 benchmark evaluates ‘tick-to-trade' network-I/O latency or the time it takes for a trade order to be received and executed.

The new AMD and Exegy STAC-T0 high-precision timestamping benchmark record was achieved with the AMD Alveo UL3524 accelerator card, a purpose-built FinTech card for fast trade execution, powered by an AMD Virtex UltraScale+ FPGA, running on the Exegy nxFramework and Exegy nxTCP-UDP-10g-ULL IP Core in a Dell PowerEdge R7525 server with AMD EPYC 7313 processors, with an Arista 7130 platform and an Arista MetaWatch 7130 device.

The AMD Alveo UL3524 accelerator features a breakthrough transceiver architecture, 780K LUTs of FPGA fabric, and 1,680 DSP slices of compute. It is designed to accelerate custom trading algorithms in hardware, where traders can tailor their design to custom algorithms and AI-enabled trading strategies.

“In ultra-low latency trading, a nanosecond can determine the difference between a profitable or losing trade,” said Girish Malipeddi, Director of Product Marketing - AECG-Data Centre, AMD. “This benchmark shows independently quantified, verified, real-world results which showcase how AMD is pushing the boundaries and possibilities in high-speed trading and financial technologies as a whole.”

Exegy provided the application consisting of the necessary FPGA IP and associated software to implement the requirements of the STAC-T0 benchmark on the Alveo UL3524 card.

“In completing this latest STAC-T0 benchmark, Exegy and AMD are thrilled to have set a record for the tick-to-trade latency,” said Olivier Cousin, director of FPGA solutions, Exegy. “This year’s STAC-T0 utilises Exegy’s FPGA development framework with the new ultra-low latency TCP-UDP IP stack, achieving the best public results to date.”