Advanced Clock-Tree Solutions

Today’s high performance equipment comprises multiple processors, FPGAs or network processors, memories, and physical layer devices supporting multi-protocol high-speed connectivity. Such systems typically call for a complex timing architecture comprising multiple reference clocks capable of coordinating the various devices and satisfying the exact clock frequency, voltage level and jitter specifications of interfaces such as PCI Express, Gigabit or 10 Gigabit Ethernet, USB3.0 and others.

Demands to minimise the complexity as well as size and cost overheads associated with such timing architectures are driving the design and development of innovative new integrated timing devices by companies such as IDT.
By replacing multiple crystals and crystal oscillators, designers can save board space and lower power consumption by using a single integrated device to generate multiple clock references. Avoiding or minimising crystal use can also mitigate procurement risks in time critical designs and deliver improved system reliability. Typically only one crystal oscillator is required as a reference. This not only reduces component costs and saves PCB real-estate, but also simplifies design.
Using an integrated multi-channel timing IC can also greatly reduce procurement risks since purchasers only need to manage the availability of one crystal part number to ensure that production can continue without delays. Other specification points that designers should consider when selecting programmable clocks include power consumption, jitter across a wide frequency range, physical size and in-system programmability.
IDT’s VersaClock 5 family of fully programmable clock generators is an example of the new generation of integrated timing devices. They differ from conventional integer-N phase-locked loop devices that provide multiple clock outputs at integer multiples of the reference input. A VersaClock 5 - 5P49V5901 can produce output clock signals at any multiple of the input reference, and with its fractional output dividers is not restricted to pure integer multiples.
In addition, each clock channel can be configured independently as dual LVCMOS outputs, or as LVPECL or LVDS outputs or the Host Clock Signal Level (HCSL) protocol as specified for PCI Express cards. The flexibility to configure clock-output channels independently, in accordance with any of these specifications, can save any need for discrete level translation ICs in a large number of applications.

The importance of Jitter
The jitter performance of programmable clock generator ICs has been improving steadily through successive generations, to meet the demands of high-speed connectivity standards. VersaClock 5 devices have class-leading RMS phase jitter of less than 0.7 picoseconds over the full 12kHz to 20MHz integration range.
High-speed interconnect standards such as 1G or 10G Ethernet and PCI Express Gen 3 specify a maximum jitter budget taking into account the contributions of all jitter sources. These include not only the clock, but also the transmitter as well as the effects of terminations and board traces. The RMS jitter budget for a 10G Ethernet connection can be as low as 1.55ps (10G BASE-R), while PCI Express Gen 3 specifies RMS jitter budget of 1.0ps for the clock. Minimising the RMS phase jitter contributed by the clock source gives the designer a greater margin to meet the link jitter budget when other contributions are taken into account.
Programmable multi-output clock generators give system designers a great deal of flexibility and can save the need for discrete level translation ICs in a lot of applications. Some applications may require a convenient integrated clock tree that can be connected in-circuit and will power up directly in the desired configuration. IDT’s VersaClock IC has four One-Time Programmable (OTP) Memory banks, which allow the device to operate in this way.
The OTP banks also enable VersaClock devices to store multiple alternative configurations. This allows engineers to use one part number in multiple projects, which can simplify procurement and inventory management, buyers can also benefit from better volume pricing. The ability to store up to four configurations also caters for applications that require frequency margining.
Power consumption is a critical parameter from both a thermal viewpoint and also helping extend battery life in the ever-increasing number of portable, battery powered devices. In general terms, integration of previously separate components into a single device has a positive effect on overall system power consumption. This holds true with integrated programmable clock generators such as the VersaClock 5 which has a total device power consumption of just 300mW with all outputs operational. In fact, VersaClock 5 compares very well not only with discrete clock sources but also with other competing integrated clocks; its core current of 30mA is about half that of alternative devices. Of course, lower power requirements also translate to fewer thermal issues which simplifies the design process. And as less provision for heat management is needed, the space, weight and cost of the finished design can be lessened too.