Boards/Backplanes

Another step for silicon capacitors

1st September 2022
Sheryl Miles
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This article originally appeared in the August'22 magazine issue of Electronic Specifier Design – see ES's Magazine Archives for more featured publications.

Empower Silicon has announced the second generation of E-Cap silicon capacitors, saving space and increasing density in wearable products and data centres. Caroline Hayes talks to Senior Vice President of sales and marketing, Steve Shultis.

Two factors are making a perfect storm for the silicon capacitor market. The first is the shortage of supply of multi-layer ceramic capacitors (MLCCs) – not many companies make them but they are considered a mainstay of circuit design. Their role is to filter signals and delay voltage fluctuations and store electric charges for the smooth operation of telecomms, industrial and consumer products. Replacing ceramic with silicon as a dielectric material is becoming popular, reports Transparency Market Research; global sales increased from 1.6bn in 2017 to 1.7bn in 2018, a CAGR of 8%.

In its Global Silicon Market Size 2022, analyst Market Watch estimated that the silicon capacitor market will be worth $1502.5m in 2022, and $1956.7m by 2028, a CAGR of 4.5%. Silicon delivers high temperature stability, making it attractive for high frequency applications. The smaller, thinner form factor, compared with MLCCs are also responsible for silicon capacitors being used in automotive and healthcare product designs.

Why silicon?

Ceramic capacitors are subject to degradation over time and subject to temperature and voltage changes. Silicon, on the other hand, is stable over these parameters. Ceramic capacitors also need space between them on a board to optimise signal performance but in November 2021, Empower Semiconductor introduced the E-Cap silicon capacitor series, of multiple discrete capacitance arrays. The technology delivers a capacitor density that is over five times that of leading MLCCs, claims the company, while offering improved equivalent series inductance (ESL) and equivalent series resistance (ESR) characteristics.

The company was packaging the silicon die in its integrated voltage regulators (IVRs) but then realised there is a broader opportunity for the technology’s use outside of the company.

Now, the company has announced the second generation, also manufactured using foundry partner, TSMC’s trench capacitor process technology. “We have increased the density and the package size is smaller,” explains Shultis. Although silicon capacitance technology is good for very high frequency applications, it is also good for high frequency decoupling, he says, and the E-Cap second generation typically targets applications that need decoupling at around 100 to 500MHz.

Capacitance consolidation

The E-Cap integrated capacitor arrays are claimed to have the highest performance and smallest size. Densities are 1.1µF/mm2, which is over twice the density of alternative silicon capacitor technologies, says Empower. Reductions in thickness, result in less than 50µm in overall height. Multiple, matched capacitance values (from 75pF to 5µF at 2V) can be integrated into a single die and form factors can be customised for a specific application in terms of space and height requirements.

This goes beyond replacing one-for-one, says Shultis. “You can consolidate the entire network [of decoupling capacitors] onto a single die with multiple connectors. The significant consolidation of the space and the size is there. This technology is absolutely ideal for saving space in high performance applications.” This offers a design advantage in, for example, data centres, where there are large decoupling networks for the power management performance.

“We take it to a different level,” declares Shultis. “We can take the whole [power decoupling capacitor] network and put it on a single die with multiple connectors.”

There is a choice of packaging options: bumps or copper pads. The nature of the bump package is that there is less material, particularly copper, to connect to the PCB or substrate, explains Shultis, and there is therefore less resistance. Copper pads, on the other hand, are easier to work with for assembly but performance is lower with regards to ESR in particular, in comparison with the bump package.

The 100-500MHz range means that E-Cap is suitable for power management in processors used in IoT nodes, in wearable devices, such as AR/VR glasses and smart watches as well as in data centre processors.

The E-cap arrays are primarily custom built although the company offers some as standard products. Working with a customer for a specific development, which may include multiple configurations on the same die, typically takes two to three months, says Shultis. The company expects to introduce more arrays as standard products by the end of the year.

 

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