SureCore supports development of chip for AI

It has already been demonstrated in more mature nodes, and the 16nm FinFET variant of sureCore’s PowerMiser IP incorporates the company’s power saving technologies to deliver world-class results.

“We are delighted to hear that the team at KU Leuven has achieved significant improvements with our ground-breaking PowerMiser SRAM IP, which we created to deliver unparalleled dynamic and static power performance," said Paul Wells, CEO, SureCore.

PowerMiser is a low-power SRAM IP that has been developed for Edge devices that require high computational loads when active as well as minmal operating and standby power consumption. It can reduce dynamic power by up to 50% and static/leakage power by up to 20% compared with foundry and other SRAM solutions, offering savings across the full process, voltage, and temperature range.

“People forget that the initial drivers for the 16nm node were mobile and HPC solutions, and hence most of the IP developed for this node was optimised for performance not power," added Wells. "Today 16nm could almost be considered to be a mature node with many millions of devices in the field. Forward-thinking application developers are now looking to exploit this node’s improved density, leakage and power characteristics, especially for wearables, medical and Edge AI devices. This is where our PowerMiser SRAM can bring huge benefits by enabling challenging power budgets to be delivered.”

“We licensed sureCore’s PowerMiser IP because we wanted to create a novel neural processing accelerator chip for AI applications. The chip has very high computational processing needs, and, of course, such devices naturally also have significant power consumption characteristics. We were very impressed that the sureCore solution could go so far in terms of power savings," said Professor Wim Dehaene from KU Leuven.

PowerMiser is available in 28nm, 22nm and 16nm process nodes, and later this year sureCore plan on releasing a 7nm variant.