Emulation platform software added to qualification programme

The certification extends Mentor’s leadership in functional safety assurance and hardware emulation technology, while helping chip designers meet and exceed the increasingly stringent safety and quality requirements of the global automotive industry.

Representing Mentor’s twenty-second ISO 26262 product qualification, these newest additions to the Mentor Safe programme underscore the company’s commitment to securing the functional safety qualification of critical documentation for all signature members of its electronic hardware and software design solutions portfolio.

“As demand for automated driving and sophisticated ADAS systems continues to transform the global automotive industry, the world’s leading carmakers and their suppliers increasingly require pre-qualified design automation technologies and documentation to speed time-to-market and ensure optimal cost efficiency,” said Eric Selosse, Vice President and General Manager of the Mentor Emulation Division. “With the Mentor Safe ISO 26262 qualification programme, Mentor is answering the call by delivering platforms and solutions that help streamline and simplify the development, design and creation of automotive-grade ICs.”

Mentor’s Software Tool Qualification Reports provide documentation including assumed use cases and evidence that a software tool is suitable to be used for any Tool Confidence Level (TCL) activity or task required by ISO 26262. SGS-TÜV Saar has certified the ISO 26262 compliance of these reports for the following software elements of the Veloce Strato emulation platform:

• The Veloce Strato OS, which enables high quality verification of system-level, RTL and GL hardware descriptions using a wide range of advanced technologies and methodologies. It allows users to manage the entire verification process, measure progress metrics, and use advanced stimuli to attain coverage targets quickly. Veloce Strato OS allows users to compile and simulate synthesizable hardware models written in VHDL, Verilog and SV, as well as comprehensive non-synthesizable testbench environment models written in VHDL, Verilog, SV, C, C++, and SystemC.
• The Veloce Fault App, which allows users to inject faults into a design to mimic random environmental events that can occur and cause faulty operation of the circuit. The application allows customers to test and assess their design’s vulnerability to safety system failure and protect it before issues arise.
• The Veloce Coverage App, which lets emulation users employ assertion coverage, functional coverage and code coverage capabilities to collect statistics during an emulation run.
• The Veloce DFT App, which accelerates design-for-test verification for complete validation of test vectors and DFT logic prior to tape-out, boosting confidence, reducing risk, and speeding chip bring-up.