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Synchronization of JESD204B Giga-Sample ADCs using Xilinx Platform for Phased Array Radar Systems

Texas Instruments

This system level design shows how two ADC12J4000 evaluation modules (EVMs) can be synchronized together using a Xilinx VC707 platform. The design document describes the required hardware modifications and device configurations: including the clocking scheme. Example configuration files are shown for each EVM. The FPGA firmware is described and the relevant Xilinx IP block configuration parameters are shown. Data taken on the actual hardware is shown and analyzed: showing synchronization within 50 ps without characterized cables or calibrated propagation delays.

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Demonstrates a typical phased array radar sub-system by showing synchronization of JESD204B giga-sample ADCsThe LMK04828 clocking solution used is described in detailTest results show synchronization within 50 ps without any characterization of cables or calibration of propagation delaysXilinx firmware development is discussed to offer a clear understanding of the requirementsThis sub-system is tested and includes example configuration files