Application Notes
Achieving Maximum Speed on Parallel Buses With Gunning Transceiver Logic (GTLP)
Texas Instruments
Published : 05 Apr 01
Description
This application report compares two approaches for synchronous bus-system designs. The focus of the report is the comparison of a system using central-synchronous system clock (CSSC) with a system operated with a source-synchronous system clock (SSSC).The basic characteristics of lines key factors that influence the bus line delay and the impedance of bus lines are described.The theoretical
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