Next-gen superjunction MOSFETs deliver lower EMI & RDS(ON)

As with the previous DTMOS IV semiconductor technology, DTMOS V is based on a single epitaxial process involving ‘deep trench etching’ followed by P-type epitaxial growth.  The deep trench filling process results in a narrowing of cell pitch and a lowering of R_DS(ON) when compared with more conventional planar processes. Toshiba’s deep trench process allows an improved thermal coefficient of R_DS(ON) compared to conventional super junction MOSFETs using multi epitaxial growth process

With DTMOS V, Toshiba has been able to reduce R_DS(ON) of the DPAK TK290P60Y by up to 17% compared with the lowest R_DS(ON)available from the TK12P60W DTMOS IV MOSFET. The company has also further optimised the trade-off between switching performance and EMI noise

DTMOS V MOSFETs will simplify the design and improve the performance of power conversion applications, including switching power supplies, power factor correction (PFC) designs, LED lighting and other AC/DC applications. The first MOSFETs based on the fifth generation process will offer ratings of 600V and 650V and be supplied in DPAK (TO-252) and TO-220SIS (smart isolation) packaging. Maximum ON resistance ratings will range from just 0.29Ω to 0.56Ω.