Ericsson Extends Vertical-Mount Voltage Regulator Series for Space-Critical Applications

The migration from single-core to multi-core processors and advanced FPGAs, in addition to the increasing trend for system upgrades with new boards featuring additional features, has led to increasing amounts of functionality being implemented on board-level designs. Designers now have to assign board-allocation priorities to ‘core’ components such as microprocessors and limit the space available to ‘peripheral’ devices such as the voltage regulator.

The 12A BMR462-SIP, 20A BMR463-SIP and 40A BMR464-SIP meet these demands to save valuable board space for core components, as they enable vertical mounting – also known as single in-line packaging (SIP), which is often used for devices such as memory chips, voltage regulators and other control boards. The SIP approach means the BMR462-SIP and BMR463-SIP offer footprints of 1.58cm2 and 1.99cm2, respectively, making them ideal for space-critical applications. The primary applications for these devices are network routers, data storage and AdvancedTCA (Advanced Telecommunications Computing Architecture) boards; additionally their low height of 15.6 mm makes them suitable for 15mm narrow-pitch applications.

“These additions to the 3E family makes Ericsson the first to offer a wide range of PMBus-compliant digitally controlled point-of-load converters in three different footprints in through-hole, single-in-line and surface-mount versions,” said Patrick Le Fèvre, Marketing and Communication Director of Ericsson Power Modules. “The high level of flexibility offered by this advanced power module family will aid designers to meet demands for high performance in space-critical applications.”

Both devices offer 66W of power, input voltage from 4.5V to 14V, and typical power efficiency of 97.1% at 5V input, 3.3V output and half load. The BMR462-SIP and BMR463-SIP deliver power densities of 38W/cm2 and 33W/cm2, with dimensions of 20.8 x 7.6 x 15.6 mm (0.82 x 0.30 x 0.612 in) and 26.3 x 7.6 x 15.6 mm (1.035 x 0.30 x 0.612 in), respectively.

The BMR462-SIP and BMR463-SIP are based on Ericsson’s leading-edge digital-core controller combined with the latest MOSFET technology and built-in energy-optimization algorithms that contribute to significantly reducing energy consumption and power dissipation and also deliver an impressive amount of features and level of flexibility. The voltage regulators can be configured and monitored via the standard PMBus communication protocol and the company’s intuitive graphical user interface offering designers the ability to fully optimize power management in high board-density applications.

Most power converters use synchronous rectification to optimize efficiency over a wide range of I/O conditions. However, at light loads the synchronous MOSFET will typically sink current and introduce additional energy losses associated with higher peak inductor currents, resulting in reduced efficiency. The device’s adaptive diode emulation mode turns off the low-side FET gate drive at low load currents to prevent the inductor current from going negative, reducing the energy losses and increasing overall efficiency.

The two devices also offer a synchronization feature that allows several regulators to be locked to a common switching frequency to eliminate beat frequencies. This reduces EMI filtering complexity and the number of external components needed. Additionally, phase spreading reduces input capacitance requirements, and hence losses, because the peak current drawn from the input supply is spread over the whole switching cycle.

The BMR462-SIP and BMR463-SIP also feature comprehensive circuit protection including over-temperature protection (OTP); output short-circuit protection; output over voltage protection (OVP); and input under voltage lockout (UVLO).

Ericsson was the first company to launch digitally controlled POL (point-of-load) regulators based on a digital core controller. Through close cooperation with board and systems designers, the company was the first to release a 21st century power architecture that can be fully integrated into the rest of the digital chain of processors and associated components.