TI delivers three high-performance clock buffer families with industry’s lowest additive jitter

These families of clock distribution buffers also save customers board space with small-footprint QFN and TSSOP options. In addition to supporting customer’s general-purpose clock buffering and distribution needs, these devices also meet stringent additive jitter requirements for wireless infrastructure, data communications and telecommunications, medical imaging and industrial applications.



Key features and benefits of the LVCMOS, LVDS and LVPECL clock buffer families



1) CDCLVC11xx clock buffer family for LVCMOS output



· Low-skew, low-additive jitter buffers generate 2, 3, 4, 6, 8, 10 and 12 copies of LVCMOS clock outputs from a single LVCMOS input.



· Very low-additive jitter of less than 100 fs RMS (12 kHz – 20 MHz) improves clock signal quality by nearly 10 times over the competition.



· Low output skew of 50 ps, maximum, provides up to five times better timing control among all outputs.



· Package modularity improves flexibility for various output configurations and simplifies board layout for multiple output requirements.



2) CDCLVD12xx/21xx clock buffer family for LVDS output



· Generates 4, 8, 12 or 16 copies of LVDS clock outputs from one of two selectable LVCMOS, LVDS or LVPECL inputs.



· Very low-additive jitter of less than 300 fs RMS (10 kHz – 20 MHz) improves clock signal quality by nearly three times over the competition.



· Low output skew of 20 ps, maximum (within same bank), delivers up to 60 percent better timing control among all outputs.



· Universal input support eliminates the need for additional external discretes for signal level translation.



· Small package options in QFN-16/28/40/48 saves board space by up to 600 percent compared to competitive devices.



3) CDCLVP12xx/21xx clock buffer family for LVPECL output



· Generates 4, 8, 12 or 16 copies of LVPECL clock outputs from one of two selectable LVCMOS, LVDS or LVPECL inputs.



· Very low additive jitter of less than 100 fs RMS (10 kHz – 20 MHz) improves clock signal quality by 10 times over the competition.



· Low output skew of 15/20/25/30 ps maximum for up to 40 percent better timing control among all outputs.



· Universal input support eliminates the need for additional external discretes for signal level translation.



· Small package options in QFN-16/28/40/48 saves board area by up to 600 percent compared to competitive devices.