SuperH family addition from Renesas Technology

The SuperH family has already launched products for other applications with up to 2.5Mbytes, so a new product with 1Mbyte of MONOS is a relatively easy step for Renesas. However, this provides a significant leap for European motor control and inverter customers. The typical code size for a high-end drive or inverter application in Europe is currently somewhere in the region of 384kbytes of code but growing at an alarming rate. The shape of motor control applications is also changing from a dual MCU to a single MCU solution and this is putting pressure on the code size. In turn, this is making European system designers consider using external memories and ROM-less devices because microcontrollers with up to 1Mbyte of embedded flash and dedicated motor control peripherals were previously not available.

The SH7286 device offers a comprehensive MTU2 timer unit with six channels of 16-bit timers, support for up to 16 input capture/output compare functions, and a three-phase PWM capability for electrical motors. Additional motor control features are enabled by a quadrature encoder feedback capability and a special channel that can measure dead times at the power stage, thus enabling both the shortest possible dead times for highest efficiency and safe, non-destructive operation of the power stage. The MTU2 also incorporates additional safety features with its Port Output Enable (POE) pins that provide a faster and more deterministic response time to ensure safe quick shutdown of the motor. Also included is an MTU2S peripheral, this is simply a subset of the MTU2. This means that the SH7286 can drive two vector controlled industrial inverters simultaneously.
The IC includes three ADCs with four channels each, 12-bit resolution and 1.0us conversion time. Each ADC can be triggered by the MTU2 with an additional defined delay time to support algorithms such as single-shunt motor drive.

For a product that is offering the capability of combining the functionality of the two MCUs in a motor control system communications is an obvious and important question. The SH7286 offers a CAN module, USB2.0 module, five SCI channels, one SSU (Synchronous Serial communication Unit) channel and one IIC channel.

The device makes use of the powerful SH-2A core. This core, an enhanced version of Renesas’ SH-2 core and having a superscalar architecture, has two execution units in the pipeline, allowing two instructions to be processed concurrently and code can be executed up to twice as fast as the CPU clock. In addition, its Harvard-based architecture ensures that no bus conflicts occur between instruction fetch and data access. The SH-2A also features the addition of an optional Floating Point Unit (FPU) and although not featured on the SH7286, provides an upgrade path for codes needing faster DSP functionality.

The core’s CPU registers are now arranged in “banks”, with the 19 registers being mirrored 15 times. Using this technique, an interrupt subroutine can use a second set of registers leaving the current ones ready for use upon return from the interrupt subroutine. This means that the registers don’t need to be popped onto and back from the stack, providing a quicker return from the interrupt subroutine. As a result, the response time to an interrupt request (IRQ) is as quick as a simple branch instruction: Just 6 cycles!

The device is complimented by, a watchdog timer, two channels of compare-match timers, 32k or 24kbytes of RAM and comes in two 176pin packages (either 24x24mm 0.5mm pitch or 20x20mm 0.4mm pitch) that operate at 3.0V to 5.5V.