Silicon Laboratories claims Industry¹s Highest Integration Isolated Gate Driver

Based on Silicon Laboratories’ proprietary RF isolator technology and advanced CMOS gate driver design, the ISOdriver family offers higher reliability, increased noise immunity and 50 percent PCB area reduction compared to competing approaches. Traditionally, power system designers rely on expensive, complex multi-die optocouplers that use exotic process technologies and require a discrete bill-of-materials - including an external FET driver. By integrating the isolator and driver into a single chip, the ISOdriver external BOM is reduced to only three capacitors and a diode, allowing an isolated high-side/low-side or dual low-side driver solution that occupies only 200 mm2.

The Si823x ISOdriver family also offers a number of performance improvements over optocoupler-based solutions. As the only isolated, high-side, low-side, 4 Amp driver available, the ISOdriver family delivers significant improvements in MOSFET turn-on and turn-off times. Less power is wasted during a FET switching cycle, enabling higher efficiency supplies. Integrated overlap protection also improves efficiency by preventing high-side and low-side MOSFETs from being on at the same time. Compared to typical opto-isolator based solutions with propagation delays of hundreds of nanoseconds or longer, the ISOdriver’s shorter propagation delay of 50 ns (max) increases timing margins and improves control response for better overall system performance and reliability. Because the ISOdriver devices are designed in CMOS, they do not suffer from the performance drift over time and temperature of optocoupler-based solutions. The ISOdriver family’s unique CMOS-based design has the added benefit of providing tighter tolerances on unit-to-unit variations, eliminating the need for factory screening or calibration after system assembly.

In addition to performance, integration and reliability advantages, the Si823x family features programmable dead-time, allowing users to optimize efficiency. Integrated under-voltage lock-out (UVLO) circuitry on both the input and output sides of the isolated driver prevents erroneous FET driver switching when input voltages are low during system start up or shut down, thus preventing damage to the supply.

“Power designers face a number of challenges when designing sophisticated, high-efficiency power delivery systems,” said Dave Bresemann, vice president of Silicon Laboratories. “By offering higher functional integration coupled with significant performance enhancements over traditional solutions we’re solving a key customer problem.”