RFCMOS ASIC platforms simplify implementation of advanced RF SoCs

Toshiba’s latest RF-CMOS technologies and services support the integration of RF, analogue and complex digital baseband and processor functions into a single chip. As a result they are ideally suited to fabless chip makers looking to deliver advanced solutions for Near Field Communications (NFC), Wide Area Networks (WANs), digital broadcast, telemetry and many other wireless communications applications.

Available at the 130nm, 90nm, 65nm and 40nm process nodes, Toshiba’s RF technology combines mature baseline CMOS processes with a fully featured RF Process Design Kit (PDK). The 130nm, 90nm and 65nm processes are characterized by high ft ratings of 90GHz, 140GHz and 180GHz respectively. The RF module enables on-chip integration of passive elements such as MIM capacitors; junction and MOSFET varactors (deep N-well, single-end and differential); half-turn differential or symmetrical inductors; and mid-range poly resistors with zero temperature coefficients. Junction capacitors and parasitic devices such as NPN transistors are also available.

To speed the development of RF SoCs, customers can choose to use Toshiba’s ‘hybrid’ ASIC / COT model. In this model the flow is divided into two – one for the digital baseband processor and the other for the analogue and RF elements. For the RF- and analogue elements, the customer implements the GDSII based on the RF-PDK, with Toshiba’s involvement to ensure success in manufacturing and testing. The customer applies its expertise to physical design of the value-added elements of the macro cell, and Toshiba actively provides feedback on process-dependent layout considerations. Once the macro cell layout is frozen, all manufacturability and yield-assurance rules will have been followed, and downstream re-spins avoided.

For the digital portion of the chip, an RT-level or gate-level netlist is accepted and the GDSII for the digital portion is implemented by Toshiba, as in a standard ASIC flow. Standard ASIC libraries, SPICE DFM/DFY models and package parasitics are part of the design environment. In addition, proven IP elements, such as, connectivity functions (HDMI, Generic SerDes, PCI-Express, SATA, USB) and A/D, D/A, PLL, SRAM, ROM, I/O, ESD and latch-up structures are available for integration into the digital baseband. Value-added place and route services are performed that take into account DFM/DFY considerations.

Lastly, the analogue- or RF blocks designed by the customer are integrated into the top-level layout. After the SoC layout is complete, the customer signs the project off based on the verification reports provided.