RF Engines Ltd (RFEL) announces new CORDIC IP design

‘CORDIC’ stands for COordinate Rotation DIgital Computer and is an algorithm (or set of algorithms) that is frequently used in practical signal processing applications for calculating a wide range of mathematical functions including logarithmic, hyperbolic and trigonometric functions. The ‘CORDIC’ is commonly used, for example, in signal processing for radar systems, electronic warfare systems, and in linearisers for power amplifier designs.



The CORDIC algorithm has long been recognized and used in electronic systems design, but the continuing trend towards intensive signal processing on FPGA has revealed limitations in how to efficiently implement the design on FPGA devices and, more specifically, the ability to trade-off specific FPGA resources for its optimal implementation.



Typically, the CORDIC implementations that are generally available from mainstream FPGA vendors are heavily biased towards the use of the FPGA’s logic resources, compared with the use of the DSP and memory block resources. This heavy usage of the logic resources can often mean that, with a complex digital receiver front-end design, there are simply insufficient logic resources available in the FPGA to comfortably accommodate the logic-based CORDIC and still achieve the required FPGA clock rate.



The new RFEL ‘Vector Rotation/Translation’ CORDIC design addresses this issue and allows implementations which otherwise would be impracticable. The key innovation is in the design of the vector rotation for the polar-to-rectangular co-ordinate transformation and vice versa, and the RFEL approach utilises a proprietary technique to more efficiently exploit the appropriate FPGA resources.