Jitter-attenuating clock multiplier IC is a first says Silicon Laboratories

The high-performance Si53xx is the first clock multiplier to generate any output frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz from any input frequency between 2 kHz and 710 MHz. The ultra-low jitter generation of the Si53xx rivals traditional analog PLLs built discretely using expensive voltage-controlled crystal oscillators (VCXOs) or voltage-controlled SAW oscillators (VCSOs). The Si53xx family features an integrated loop filter with selectable bandwidths, allowing designers to change the loop bandwidth without changing components and enabling jitter performance optimization at the application level.



The Si53xx integrates a rich set of features on-chip, reducing the bill-of-materials (BOM) while optimizing jitter performance. The Si53xx includes an ultra-low phase noise, frequency-agile voltage-controlled oscillator (VCO), loop filter, phase detector, divider and buffers. Traditional PLL designs require discrete components, creating noise entry points between circuit elements. By eliminating the noise entry points, the Si53xx simplifies the task of achieving ultra-low jitter performance. Additionally, the Si53xx family supports up to four clock inputs and five differential clock outputs, eliminating the need for external muxes and clock distribution buffers traditionally used in complex timing subsystems of modern communications equipment.



The Si53xx family simplifies the design and supply chain issues of modern timing architectures. Unlike traditional PLL implementations that only operate over a limited frequency range, the Si53xx family can be digitally reconfigured to operate over a broad range of frequencies, removing the need for multiple expensive VCXOs or VCSOs and easing design reuse. The Si53xx family also supports hitless switching to absorb phase differences between input clocks during a clock switchover. In addition, the Si53xx uses standard IC manufacturing technology, which can reduce lead times to four weeks compared with the long, unpredictable lead times associated with VCXO- and VSCO- based clock circuits.



“The any-rate capability of the Si53xx family broadens the addressable market of our timing solutions,” said David Bresemann, vice president of Silicon Laboratories. “The combination of the any-rate precision clock family and our oscillator and voltage controlled oscillator products creates the industry’s most comprehensive portfolio of frequency-flexible, low-jitter timing solutions.”