Clock IC First To Harness GPS Signals For Synchronization

Developed for remote optical and wireless network nodes, cable infrastructure and data communications equipment, the AD9548 clock generator/synchronizer eliminates the dedicated oscillators, phase-locked loops, and other clock recovery circuitry communications systems previously required to generate clock signals synchronized to the widely available 1-pps GPS standard. Using the AD9548 to leverage GPS signals simplifies and shortens the design process while providing a lower-power timing reference.

The AD9548 includes a digital PLL that up-converts the 1-pps GPS signal while reducing input-time jitter or phase noise associated with the external references to as little as 300 femto seconds. The clock distribution section provides four output drivers. Each driver is programmable either as a single differential LVPECL/LVDS (low-voltage positive emitter-coupled logic/low-voltage differential signalling) output or as pairs of single-ended CMOS (complementary metal-oxide semiconductor) outputs. Each of the four outputs has a dedicated 30-bit programmable post divider enabling the generation of multiple different output frequencies. An integrated reference clock multiplier allows for system clock references as low as 4 MHz while still supporting outputs of up to 450 MHz. The AD9548 also includes a digitally-controlled loop filter programmable to as low as 1-mHz (1x10-3), as well as manual and automatic holdover circuitry that continuously generates a low jitter, valid output clock even when some, or all, references have failed.