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Clock Buffers Achieve 75-fs and 100-fs Jitter Performance and 9-ps Skew

5th June 2009

Analog Devices

ES Admin

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Datasheet

Analog Devices has announced 6- and 12-channel, compact clock buffers for high-speed applications requiring low jitter. ADI’s 12-channel ADCLK954 LVPECL and ADCLK854 LVDS/CMOS and 6-channel ADCLK946 LVPECL and ADCLK846 LVDS clock fanout buffers provide up to four times as many clock channels on a single chip, with better combined jitter and skew performances than competing devices in their category. Jitter is as low as 75 fs (femto seconds) for ADI’s LVPECL (low voltage positive emitter coupled logic) fanout buffers and 100 fs for its LVDS (low voltage differential signaling)/CMOS fanout buffers. In addition, the ADCLK9xx clock buffers offer an extremely low 9-ps (pico second) skew. The ADCLK854 clock buffer also offers 24 CMOS (complementary metal oxide semiconductor) channels.

With these specifications, the clock buffers are effective for clocking high-speed ADCs (analog-to-digital converters) and DACs (digital-to-analog converters) and are suitable for high-performance applications, such as wireless infrastructure equipment, medical imaging and industrial applications that require high speed, high channel density and outstanding timing performance.

The 6- to 12- additional clock channels reduce component count and board space while simplifying high-speed signal-chain design and lowering overall bill-of-materials costs.

The industry-leading jitter and skew performance that the 12-channel ADCLK954 and the 6-channel ADCLK946 LVPECL fanout buffers deliver allows design engineers to achieve better SNR (signal-to-noise ratio) from an ADC or DAC. The 4.8-GHz ADCLK954 has two selectable differential inputs via the IN_SEL control pin. Both inputs are equipped with 100-ohm on-chip termination resistors and may operate with either differential or single-ended clock sources.

The 12 LVDS/24 CMOS-channel ADCLK854 and 6 LVDS/12-CMOS-channel ADCLK846 provide high timing performance at 100-fs jitter. All the clock buffers allow design engineers to benefit from the full resolution and performance of high-speed ADCs and DACs while maintaining low power of 12-mW per channel at 100-MHz operation. The ADCLK854 offers two selectable inputs and a sleep-mode feature. The IN_SEL pin-state determines which input fans out to the outputs. The SLEEP pin enables a sleep mode to power down the device. The inputs accept various single-ended and differential logic levels, including LVPECL, LVDS, HSTL (high speed transceiver logic), CML (current-mode logic) and CMOS.