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Analog Devices Introduces Simplified Clock Generator Architecture

24th February 2009

Analog Devices

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Datasheet

Analog Devices has introduced a clock generator that simplifies clock design and reduces the need for oscillators in multi-standard networking and communications infrastructure systems. The AD9551 clock generator features a new, simplified architecture engineered by ADI that can generate and translate multiple precision network clock frequencies, which enables the replacement of as many as five oscillators. Oscillators support forward error correction (FEC), holdover, switchover, and precise frequency generation—functions that are essential in network switches, routers, and line cards.

In addition to saving board space, the AD9551 provides more accurate and reliable performance than discrete oscillators, while reducing system development time and complexity by making it easier for networks relying on incompatible standards to share and transfer data.

The AD9551 clock generator accepts one or two reference input signals and generates one or two output signals that are harmonically related by a programmable factor of 1 to 63. Precisely translating the reference frequency to the desired output frequency, it includes input receivers and output drivers that are capable of either single-ended or differential operation. On-chip reference monitoring and switchover circuitry internally synchronise the two references to prevent phase perturbations at the output in the event of a reference failure.

Should either or both references fail, the AD9551 maintains a steady output signal with no phase disturbance on the output. The device relies on an external 26-MHz crystal (nominal) and the internal digitally-compensated crystal oscillator (DCXO) of the first of two cascaded fractional-N phase-locked loops (PLLs) to provide a clean reference for the second PLL, and to hold the output frequency in case of reference failure. The second fractional-N PLL enables fine precision output frequency tuning with low phase noise. The AD9551 provides a serial-peripheral interface (SPI) port, and pin-selectable pre-set divider values that offer an assortment of frequency ratios, including all the standard rates for Gigabit Ethernet (644.53125 MHz), 10 Gigabit Ethernet (625 MHz), SONET/SDH (622.08 MHz), and Fiberchannel (657.421875 MHz) as well as the established FEC ratios (15/14, 239/237, 239/238, 255/237, 255/238).

In addition to network clocks, including the AD9520, AD9522, ADCLK905, ADCLK907 and ADCLK925 Ultrafast SiGe ECL Clock/Data Buffers and the Ultrafast, SiGe, Open-Collector HVDS Clock/Data Buffer, ADI makes a wide range of components addressing all aspects of networking and communications system design, from power management to analogue and mixed-signal solutions.