Achronix demonstrates 1066Mbps DDR3 reference design on new speedster plug-in card development board

The SPD60 FPGA has four embedded DDR3 controllers. A full-speed (533 MHz, 1066 Mbps), full-width (72-bit) DDR3 interface can be built using no programmable logic resources. It comes complete with reference design RTL code and documentation, which can be modified as required. Neither the controller nor the reference design requires any license fee.

The development board is designed for systems engineers who need access to both high-end 10.3 Gbps SerDes and DDR3 memory in a compact platform. SPC60 is ideal for applications where there is a growing need for high-performance (both logic and interconnect), such as in the high-end networking, signal processing, and high-performance computing markets.

“The combination of extreme logic throughput and DDR3 memory bandwidth in our Speedster FPGAs enable engineers to create high-performance designs never before achievable,” said Yousef Khalilollahi, Achronix vice president of worldwide sales and marketing. “By embedding the 1066 Mbps DDR3 controllers in the FPGA and offering a complete DDR3 reference design, we have removed the burden of FPGA memory interface implementation and verification.”

With the SPC60 development board, designers can exercise the full performance of the Speedster device, run prepared designs provided with the kit, configure the device with a new design, and debug that design on a common platform. Achronix-specific and industry-standard development tools are provided, along with a collection of standard reference designs.