Winbond joins UCIe Consortium to support chiplet interface standardisation

This open industry standard defines interconnect between chiplets within a package, enabling an open chiplet ecosystem and facilitating the development of advanced 2.5D/3D devices.

A leader in high-performance memory ICs, Winbond is an established supplier of known good die (KGD) needed to assure end-of-line yield in 2.5D/3D assembly. 2.5D/3D multichip devices are needed to realize the exponential improvements in performance, power efficiency, and miniaturisation, demanded by the explosion of technologies such as 5G, Automotive, and AI.

By joining the UCIe Consortium, Winbond supports interconnect standardisation that simplifies system-on-chip (SoC) design and eases 2.5D/3D back-end-of-line (BEOL) assembly. The UCIe 1.0 specification provides a complete standardised die-to-die interconnect with a high-bandwidth memory interface, facilitating SoC-to-memory interconnection for low latency, low power, and high performance. Ultimately, standardisation will power market growth in advanced multichip engines by accelerating the introduction of higher-performing products that deliver increased value for device makers and end users.

Winbond’s 3D CUBE as a Service (3DCaaS) platform gives customers a one-stop shopping service. It includes 3D TSV DRAM (aka CUBE) KGD memory dies and 2.5D/3D BEOL with CoW/WoW optimised for multichip devices, in addition to the consulting service. That is to say; customers can have more completed and comprehensive support from CUBE and with extra value like Silicon-Cap and interposer. Winbond has been committed to providing the best product solution, and by joining the UCIe Consortium is positioned to deliver standardised 3D DRAM and 2.5D/3D BEOL services to customers.