Frequency Synthesis and Clock Generation for High Speed Systems
Frequency synthesis and clock generation are now key elements in all aspects of high speed data acquisition and RF design. In this session, the primary types of frequency synthesizers—phase-locked loops (PLL) and direct digital synthesizers (DDS)—are discussed, along with the applications for when each is appropriate.
Also covered are detailed aspects of synthesizer design. Other applications, such as clock distribution and translation are addressed, and problems associated with poor clocking are identified. Examples of poor clocking are shown, along with the results of doing it properly. Presented by Mike Curtin, Applications Engineering Manager
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