NSITEXE chooses Imperas RISC-V for automotive IP

RISC-V is an open ISA (Instruction Set Architecture), which permits many configurations and options for processor implementation and microarchitectural features. The vector instruction extensions support complex arithmetic operations required for applications involving linear algebra, such as AI (Artificial Intelligence) and ML (Machine Learning).

Extensive test and verification is required to achieve the Automotive industry standard ASIL D safety requirement level of the ISO 26262 functional safety standard for vehicles. 

Virtual Platforms based on Imperas models and simulator allow early SoC architectural exploration as system developers map complex AI algorithms to new multiprocessor configurations. As RISC-V supports both standard instruction extensions such as vectors, as well as user defined custom instructions, the Imperas models and analysis tools support the complete flexibility and design freedoms for the front-end design flow.

As the project develops to the next phase, the hardware design verification (DV) team can use the Imperas RISC-V reference model and verification suite to validate the design before tape-out. Due to the broad range of configurations available for the vector extensions the Imperas verification suite includes a compliance validation test to ensure early compatibility with the growing ecosystem supporting RISC-V vectors.

“For the automotive market our customers expect the highest standards of quality and design assurance,” said Hideki Sugimoto, CTO of NSITEXE. “NSITEXE selected the Imperas Vector Extensions Compliance test cases and RISC-V Reference Model as a foundation for our simulation-based design verification (DV) plans.”

“Virtual platforms enable the essential early development of software well before RTL or silicon prototypes are available, which dramatically accelerates the time to market,” added Nobuyuki Ueyama, President of eSOL TRINITY. “In addition, for the next generation of automotive AI designs, the early architectural exploration of the SoC helps validate the system design and becomes the reference model for RTL verification.”

Simon Davidmann, CEO at Imperas Softwarecommented,“The RISC-V vector instruction extensions offer a broad set of parameterisable features, functions and options that can be fine-tuned for the target application. Two of the most critical requirements of a professional DV plan are the reference model for functional verification and test suite for validation and ecosystem compliance. We are proud to support the engineering team at NSITEXE with the Imperas golden reference model for RISC-V, including vector extensions.”

The latest RISC-V vector instruction extension specification is fully implemented within the Imperas RISC-V reference model.