Agile Analog launches digitally wrapped analogue IP subsystems

These innovative, digitally wrapped subsystems reduce the effort required to integrate multiple analogue IPs into any ASIC by allowing the IP to be dropped straight into a digital design flow and connected via a standard peripheral bus, such as AMBA APB. The subsystems look just like a normal block of digital IP with the standard interfaces that engineers would expect, making them easy to understand and handle. As a result, time to market, costs and risk are radically reduced. Initially, the company is introducing three subsystems: agilePMU for power management, agilePVT - PVT sensor, and agileSMU for sleep management.

Chris Morrison, Director of Product Marketing at Agile Analog, said: “I’m delighted to announce our first three subsystems. Customers are always looking for ways to reduce time to market, cost, and risk, and our new, digitally wrapped subsystems do just that. Crucially, customers no longer need to deal with the complex mixed-signal boundary between analogue and digital, drastically decreasing their design effort and the risks often associated with integrating a complex array of analogue IP.”

The IP blocks within a subsystem are all from Agile Analog’s existing portfolio of customisable analogue IP. This allows each block within the subsystem to be customised to the customer’s exact requirements whilst sitting within the overall digital wrapper. As with all Agile Analog IP, the digitally wrapped subsystems are process and foundry agnostic, and each design is optimised for the customer’s specific PDK. Integrating IP within a subsystem further enhances the customer’s design by removing duplicate analog functions, reducing design rule checking (DRC) requirements, and optimising interconnects. These lead to increased noise immunity, lower power consumption and smaller area.

Another key benefit to the customer is that all the verification requirements of the analogue to digital, mixed-signal, boundary are performed by Agile Analog. This significantly reduces the customer design and verification time, de-risks the design process, lowers the cost of licensing mixed signal design tools, and simplifies integration. Customers can now add analogue features to provide product differentiation without needing specialist analog and mixed signal engineers, and the associated costly toolchain.

Agile Analog’s subsystems are supplied with a full set of supporting collateral, including System Verilog models for easy integration into customers’ existing digital verification flows.