The future of optical networking at OFC 2018

Massive growth in data traffic driven by cloud services and the rollout of 5G is creating challenges to keep up with burgeoning bandwidth requirements within networks.

Line card port densities in routers and switches, optical standard evolution and optical network bandwidth update are major constraints to cost effectively keep pace with bandwidth needs. The transition to 58G and 112G transceivers is an important step to deliver 400G and 800G+ data rates on the same existing footprint.

Anticipating even more demand for speed and throughput, Xilinx is demonstrating full-duplex 112G PAM4 signaling on a single lane. Industry experts regard 112Gb/s transceiver performance as necessary to address next-generation optical networking and line card densities. Customers can expect programmable devices with 112G transceivers in Xilinx’s upcoming 7nm portfolio.

“Xilinx has a long history of driving standards efforts and pushing performance limits in serial interconnect technology, and continues to do so with the industry’s first 112G PAM4 demo as well as with its 58G PAM4 solution, here today for customers to begin designing in with,” said Karl Freund, senior analyst, HPC and machine learning, Moor Insights & Strategy.

“Today’s Xilinx announcements represent a significant leap forward for network architects who continue to be challenged to improve bandwidth performance of their optical networks.”

Built on the most sought-after Virtex UltraScale+ class of devices for high-end applications, the new Xilinx transceiver architecture enables customers to effectively double the bandwidth capabilities of existing systems by combining the flexibility of programmable logic with 58G PAM4 transceivers.

These devices can operate over existing 25G backplanes, extending the life and bandwidth of current systems while paving the way for the next generation. For migration, the new devices with 58G transceivers are footprint compatible with existing Virtex UltraScale+ devices in production today.

Targeted at cloud computing, 5G networking, core networks (OTN, Ethernet) and network functions virtualisation (NFV) applications, this latest transceiver architecture will enable vendors to scale 50G, 100G and 400G ports and terabit interfaces in compact and less complex system designs.

“Networks are changing dramatically to enable faster, more flexible and more adaptable systems, and the industry is gearing up in anticipation of the change with new optics and standards,” said Farhad Shafai, Vice President, communications markets, Xilinx.

“We are proud to be leading the way in delivering the most flexible and adaptable solutions to our customers, along with production-proven silicon, a track record of quality and in tandem with the ecosystem of optics, backplanes and other key technologies in development.”

The new 58G PAM4 Virtex UltraScale+ devices include integrated PAM4 transceivers, 100GE IP blocks, and all associated FEC required for next-generation interconnect. Xilinx will demonstrate 58G and 112G PAM4 at OFC 2018 Booth #2807. Xilinx will also participate through OIF (Booth #5525) 56Gb/s interoperability demonstration.