Specialty Coating Systems to Present at IWLPC

As technology moves forward, a variety of wafer level packaging methods have been developed, which includes thin-film redistribution and bumping, encapsulated package, compliant interconnect, wafer level underfill, use of through wafer vias, wafer thinning and the ability to bond or integrate these new structures. Driven by the demand for improved integration methods, reliability and performance, innovative solutions are being explored by researchers. Some of the challenging areas include: thin wafer processing, miniaturization, issues of stiction, reducing interconnect fatigue, thermal stability and insulator formation by CVD polymers for providing integration ease and overall protection from environmental effects.

The paper will describe the characteristics and potential applications (both as structural material and possible coating applications) of high temperature vapor phase polymer (thermally stable up to 350°C and commercially available as Parylene HT) for wafer level packaging technology. Through comparison and examples, it highlights some key attributes of a relatively new, RoHS compliant, halogen free (per IEC-60754-2) polymer for its use with many components. Formed at nano and micro scale, Parylene offers solutions to many challenges that exist in the wafer level packaging technology including reliability and protection from harsh and corrosive environments. SCS also will exhibit Parylene coatings in Booth 52.