Sondrel shares system-to-silicon IC design expertise at U2U

Sondrel Verification Consultant, Hélène Wood is presenting a paper on Questa Power Aware simulations using UPF files. Simulating with UPF files is essential for checking power management implementation in a design. Hélène’s presentation is targeted towards those new to UPF, will explain what it is and include a discussion on the UPF Verification flow. The advantages and disadvantages of UPF will be covered, as will the importance of introducing UPF early in the design flow to help find any power related issues.

Gianvito Lorusso, Engineering Manager, is speaking on the use of Olympus-SoC place and route software in a large 28nm design with over 70 million nodes. He will detail the various design stages, including block development, chip assembly, low power management and clock control, reviewing how the design’s exceptional timing closure and power management challenges were overcome. His presentation includes a discussion on the ECO capability of Olympus-SoC along with the Calibre InRoute interface to achieve final design signoff before Tape Out.

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