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Silicon solution boosts performance to 1.48/2.67DMIPS/MHz

12th October 2015
Jordan Mulcare
0

Recognised as one of the most prestigious promotional events in the world, EXPO is a great opportunity to show the most innovative potential to a wider audience. Digital Core Design has been selected by the Ministry of Administration and Digitization (MAC) to present the D32PRO in a form of an interactive stand in the Polish pavilion from 12th to 18th October during Polish ICT Week at EXPO Milano 2015.

The D32PRO is a 32-bit, deeply embedded and royalty-free IP Core. This silicon proven solution, based on RISC architecture but mastered on DCD’s experience dated since 1999, boosts performance to 1.48/2.67DMIPS/MHz and 2.41CoreMarks/MHz. The minimal usable D32PRO CPU starts from 10.6k/6.8k gates when optimised for area. Dynamic power is 7μW/MHz with a 90nm process (DCD’s IP Cores are synthesisable and foundry independent). The D32PRO has been equipped with C compiler and integrated CPU configurator. This makes DCD’s CPU fully configurable, both for ultra-low energy and for power-user projects.

“Polish ICT week is a great opportunity for Digital Core Design to present its IP Core portfolio. For more than 15 years our company has been developing innovating architectures," says Jacek Hanke, CEO, DCD. "Polish ICT week at EXPO will be a chance for our company to present our latest solution to the world, the D32PRO. It’s a 32-bit, royalty-free, deeply embedded CPU, introduced in mid-September during the conference held at the Ministry of Economy in Warsaw. We haven’t forgotten that our presentation should offer something more to visitors. That’s why along with the CPU, we’ll use a special 3D hologram device to present D32PRO’s functionality. And this is just the beginning.”

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