Results of '3D Electroform Stencils for Two-Level PCBs' to be presented at IPC APEX
Photo Stencil will present results of the paper '3D Electroform Stencils for Two-Level PCBs', on Wednesday 25th February at 10:00-10:30am and 4:30-5:00pm, in room 6A, IPC APEX Expo 2015, San Diego, California. The paper was written and will be presented by Rachel Miller-Short, Photo Stencil, in collaboration with William E. Coleman, Photo Stencil, Dudi Amir, Intel, and Joseph Perault, Parmi.
The first requirement was printing solder paste for a 0.3µm µBGA with pads on two levels of the PCB separated by 175µm. The second requirement was printing flux or solder paste into a recessed area on the PCB for an embedded flip chip. The cavity depth was 350µm. 3D Electroform stencils were used for both print requirements.
Rubber, metal, slit metal and notched metal squeegee blades were tested. Print results, including paste volume and paste volume dispersion, were analysed. Study conclusions, with thoughts for additional research, will be presented at the session.
“The requirements for two-level PCBs with components on both levels have seen a recent increase,” explained Rachel Miller-Short, VP Global Sales, Photo Stencil. “Stencil printing on both levels requires special stencil and squeegee blade designs. Combining Photo Stencil's expertise in stencil design and using Parmi's solder paste inspection equipment to analyse the results, we decided to examine two requirements necessitated by these boards.”
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