JTAG Maps showcased at Utrecht event

JTAG Maps is a simple extension to the Altium Designer tool suite that allows the user/engineer to thoroughly assess the capabilities of the JTAG/boundary-scan resources on their design - before committing to layout. 

Until now engineers could often spend hours highlighting the boundary-scan nets of a design manually to assess the fault coverage that boundary-scan testing could bring a specific design.

Today the free JTAG Maps for Altium, application extension, does all this and more, freeing up valuable time, allowing a more thorough DfT and speeding time to market. 

Boundary-scan device models (BSDLs) are pivotal to any JTAG/boundary-scan process as they indicate precisely which pins can be controlled or observed by JTAG/boundary-scan. However BSDL models are not always available in a timely manner. It is necessary to enable a view of potential boundary-scan coverage without a specific BSDL.

This feature can also be used to indicate fault coverage to a connector (set to assume scan covered) or to highlight the differences in fault coverage between two equivalent parts, one with and one without built-in JTAG/boundary-scan.

The latest product on display will be an example of JTAG’s  ‘fixture embedded’ test technology - the JT 5705/FXT multi-function JTAG tester built into one the small linear series of cassette-based re-configurable fixtures of Everett Charles  Technologies (ECT).

The JT 5705/FXT is a compact, single-board test system that supports analog measurement and stimulus, frequency measurements, digital I/O, boundary-scan testing and also in-system device programming. Within the fixture multiple JT 5705/FXT tester cards can be mounted on purpose built carriers featuring the ATE industry standard ‘.

Peter van den Eijnden, MD JTAG Technologies will present on on the following topics theduring the exhibition - The Value of Boundary-Scan for todays’ hardware engineers and Lowering the costs of testing by using Boundary-Scan in the     prototype phase