Agile Analog launches first complete RISC-V analog IP subsystem at RISC-V Summit Europe

The initial subsystem includes all the analogue IP required for a typical battery powered IoT system, including a power management unit (PMU), a sleep management unit (SMU), and data converters. This unique, process agnostic, customisable and digitally wrapped analogue IP subsystem will help solve many of the issues that System on Chip (SoC) designers currently encounter, as it pairs with a RISC-V core to form a complete solution.

Chris Morrison, Director of Product Marketing at Agile Analog, explains: "The RISC-V architecture is enabling a surge of new SoC product developments, and the demand for more accessible and configurable IP solutions is increasing. One of the major challenges that digital chip designers face is in integrating the analogue circuitry to support their SoC designs."

Chris adds: "With our RISC-V analogue IP subsystem, it's possible to access the appropriate analogue IP for a specific process and foundry. This can then be integrated seamlessly with digital IP from a digital IP provider in the RISC-V space, simplifying chip design and accelerating the time to market for new RISC-V IoT applications. As with all of the Agile Analog IP, this subsystem is customisable to give the exact feature set required for the application."

Traditional analogue IP has been a major bottleneck for many years, with limited options available, and chip designers have struggled to integrate multiple analogue IP blocks, often from multiple vendors. The design and verification of the mixed-signal boundary between analogue and digital has been a particularly daunting task, as this is renowned for being time-consuming and expensive, requiring specialist knowledge and tools. However, as a result of Agile Analog's unique technology and novel digitally wrapped approach, these integration and verification challenges can be addressed and promptly resolved by Agile Analog on behalf of the customer.

This new analogue IP subsystem is verified in both analogue and digital environments, connects directly to the MCU's peripheral bus, and is supplied with a SystemVerilog model for easy integration into an SoC's existing digital verification environment.

Calista Redmond, CEO of RISC-V International, comments, "RISC-V is already seen in over 10 billion cores globally, and the RISC-V ecosystem is flourishing. It's really important that there are innovative solutions like this to help chip designers in our community to fast-track the delivery of exciting new RISC-V IoT applications."

Agile Analog will be exhibiting and presenting at the RISC-V Summit Europe 2023.