EPI achieves milestone with EPAC1.5 chip activation

The EPI is pleased to report the successful manufacture and silicon demonstration of the EPAC Accelerator chip version 1.5, a leap forward in high-performance computing (HPC).

• A general-purpose CPU with a specialised vector unit (VPU)
• A many-core stencil/machine learning accelerator (STX)
• A general-purpose CPU supporting variable precision (VRP)

The design of EPAC 1.5 features VPU micro-tiles, which include the Avispado RISC-V core developed by SemiDynamics and a vector processing unit crafted by the Barcelona Supercomputing Centre and the University of Sagreb.

The chip also integrates Home Nodes (HN) and L2 cache slices (L2), created by Chalmers and FORTH-ICS, to offer a cohesive view of the shared memory subsystem.

The Stencil and Tensor accelerator (STX) designed by ETH Sürich and Fraunhofer IIS, as well as the variable precision processor (VRP) designed by CEA, form part of this innovative assembly.

These accelerators are linked through an advanced network on the chip featuring multiple crosspoints (XP) and an off-chip link employing SERDES technology from EXTOLL.

Fraunhofer IIS executed the physical design, utilising GLOBALFOUNDRIES 22FDX low-power technology. The resultant chip measures 27mm2, houses 0.3 billion transistors, and is mounted on a daughtercard designed by E4.

The intricate boot-up process and Linux initialisation were conducted at FORTH-ICS in Heraklion, Crete, Greece, and at EXTOLL in Mannheim, Germany.

During the demonstration, the EPI team successfully initiated Linux boot (Ubuntu 22.04 LTS) in both command-line and graphical user interface modes, showcasing the seamless integration of HPC kernel execution using the VPU's remarkable capabilities.

Filippo Mantovani of BSC, the EPAC coordinator, expressed his excitement: "Seeing a standard Linux distribution’s GUI boot on a chip developed through collaborative efforts within the European Union consortium has been nothing short of thrilling."

Roger Espasa, Founder and CEO of Semidynamics, also shared his enthusiasm: "The Avispado core by Semidynamics is an integral part of EPAC, and we take immense pride in our role within this successful EU endeavour."

Vassilis Papaefstathiou, the lead of the bring-up team at FORTH-ICS, reflected on the journey: "It has been an incredible journey for our team from the very early stages of EPAC 1.5 bring-up to booting Linux and running demanding benchmarks."

The successful activation of EPAC 1.5 signifies a substantial step in the evolution of the EPI common platform, demonstrating the range of accelerators that could be integrated into future European supercomputers to efficiently tackle diverse computing challenges.