Xilinx Addresses System Integration with All Programmable SoCs at ARM TechCon 2012

In-booth demonstrations and technical sessions will highlight the broad base of end applications and design solutions enabled by Zynq™-7000 All Programmable SoCs. Xilinx will also host a panel of experts on the pressing need for data security and design security across industries.



What: ARM TechCon 2012



Where: Santa Clara, CA, Santa Clara Convention Center, Booth #515



When: Conference & Exhibits – October 30-November 1, 2012



Panels



Thursday, November 1



12:00 p.m. – 12:45 p.m., Expo Floor



Critical System Design Challenges for a Secure World: Alternative Approaches and What Remains to be Done



Join experts from Xilinx, ARM and other industry leaders as they look at alternative hardware, software and combined hardware/software approaches to system challenges such as secure boot, data encryption, tamper and failure detection, key storage, support for multiple operating systems and software stacks. Key technologies discussed will include ARM TrustZone® technology, IP cores, hypervisors, and secure boot capabilities.



Sessions



Tuesday, October 30



11:00 a.m. – 4:00 p.m., Ballroom 5



Accelerate Networking Application Development with the Xilinx ARM Cortex-A9 processor-based Mutli-core Zynq-7000 All Programmable SoC



Today's network applications are experiencing explosive traffic growth that demands fast and flexible convergence of compute & networking to secure the cloud infrastructure. This session will explore the use cases of applying the Xilinx Zynq-7000 All Programmable SoC in wired networking applications, providing solutions much faster and more customizable than alternative SoCs.



Wednesday, October 31



11:30 a.m. – 12:20 p.m., Grand Ballroom E



Real-Time and Multi-core Processors – Helping Them Work Together



This session will examine architecture techniques for increasing real-time capability in multi-core systems including use of co-processors, asymmetric multiprocessing (AMP) and FPGA programmable logic. These techniques provide implementation options for solving signal conditioning problems and facilitate meeting real-time performance requirements more predictably. Specific use cases and examples will be provided.



Thursday, November 1



10:30 a.m. – 11:20 a.m., Ballroom G



A Case Study on Mapping Physical Simulation Algorithms to Heterogeneous Computing Platforms Utilizing Multi-core CPUs, Compute Accelerators and/or FPGAs



The speakers will discuss process and implementation strategies that enable the development of custom high-performance parallel computing solutions utilizing application specific hardware units in emerging architectures with multi-core CPUs, GPUs or FPGAs such as Xilinx's Zynq-7000 All Programmable SoC. Industry experts will present a practical algorithmic case study that serves to illustrate how an algorithm can be designed, partitioned and mapped to leverage the various computational elements of a heterogeneous architecture such as an All Programmable SoC.



1:30 p.m. – 2:20 p.m., Grand Ballroom E



Accelerating Multimedia Performance of Your ARM Processor with a Co-processor



Discussion topics for this session will include different methods for attaching accelerators to processors such as the ARM Cortex™-A9 and the tradeoffs for each use case. The latter portion of the session will explore the implementation of a real-world processing problem and how software tasks were accelerated with programmable logic accelerators tightly coupled to an ARM dual-core Cortex-A9 processing system.



2:30 p.m. – 3:20 p.m., Grand Ballroom B



Low-Power and Multi-core Processing: Optimizing Performance and Power with Programmable Systems



This session examines the integration of ARM processors, power domains, clock management, and co-processing offloading into FPGAs, which enables dramatic reduction in system power for high-performance applications. These techniques yield an order-of-magnitude less power, as computational tasks requiring tens or hundreds of watts with a general-purpose processor can be managed via an ARM Cortex-A9 processor system integrated with programmable logic.



3:30 p.m. – 4:20 p.m., Ballroom G



Algorithmic Acceleration of Processing Systems Using High-Level Synthesis



This paper discusses how system designers can rapidly build efficient, high-performance, customizable single-chip processing systems using Xilinx's latest All Programmable SoC technology.



Exhibition Demos



Tuesday – Thursday, October 30 - November 1



-Image Processing –Co-processing acceleration using Zynq-7000 All Programmable SoCs on iVeia's Breckenridge Platform.

-Driver Assistance Solution – Zynq-7000 All Programmable SoC-based scalable, single-chip platform for driver assistance applications. Demonstration will showcase blind spot detection using Optical Flow.

-SYSGO Hypervisor – Three operating systems concurrently executing on the two processor cores of the Zynq-7000 All Programmable SoC. The application will visually show different scenarios: stopping and resuming some partitions, changing scheduling policy and showing impact on real-time behavior.

-Object Recognition and Tracking – Demonstration showing how Zynq-7000 All Programmable SoCs can be used in real-time applications with critical loop processing being handled in programmable logic.