VITA 78 SpaceVPX systems reach ANSI recognition

ANSI/VITA 78 defines an open standard for creating high performance fault tolerant interoperable backplanes and modules to assemble electronic systems for spacecraft and other high availability applications. Such systems will support a wide variety of use cases and potential markets across the aerospace and terrestrial communities. This standard leverages the OpenVPX standards family and the commercial infrastructure that supports these standards.

“We are pleased that SpaceVPX Systems have received VITA/ANSI recognition,” said Patrick Collier, Senior Electrical Research Engineer, Space Communications Program, AFRL Space Vehicles and Working Group Chair, VITA 78. “We were able to pull together the minds of engineers from companies around the world that have a vested interest in developing this specification for the space industry.”

“Patrick was and continues to be a great asset in getting this specification through the process,” stated Jerry Gipper, VITA executive director. “Without his leadership, energy and passion it would have been extremely difficult to complete this work effort.”

The goal of SpaceVPX Systems is to achieve an acceptable level of fault tolerance while maintaining reasonable compatibility with OpenVPX components, including connector pin assignments. For the purposes of fault tolerance, a module is considered the minimum redundancy element.

For high reliability applications, the major fault tolerance requirements are: dual-redundant power distribution (bussed) where each distribution is supplied from an independent power source; dual-redundant utility plane signal distribution (point-to-point cross-strapped) where each distribution is supplied from an independent system controller to a module that selects between the A and B system controllers for distribution to each of the slots controlled by the module; card-level serial management; card-level reset control and card-level power control.

Additional fault tolerance requirements include: matched length, low-skew differential timing/synchronisation/clocks; fault tolerant power supply select (bussed); fault tolerant system controller signal selection (bussed); dual-redundant data planes (point-to-point cross-strapped) and dual-redundant control planes (point-to-point cross-strapped).