Analysis
SynaptiCAD’s GOF fixes Logic Equivalence Check Failures - Whitepaper
SynaptiCAD’s Verilog netlist editor, Gates-on-the-Fly (GOF), has recently been updated to support easy correction of logic equivalence failures introduced during modifications to post-synthesis netlists, using equivalence check reports from either Cadence’s Conformal LEC or Synopsys’s Formality. SynaptiCAD has also published a white paper that describes how the updated GOF was used to find and fix failures identified by Cadence’s Conformal tool at a customer site.
GOF GOF graphically analyzes and edits large Verilog netlists that have been generated from a synthesis or layout tool. Netlists sometimes require changes to either meet timing closure specifications, fix functional logic bugs, or to repartition a design. Using GOF’s unique “incremental schematic” technology, you can easily find, view, and edit specific logic cones in your design on a schematic to visualize just the paths you need to see without unnecessary clutter.
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