Spreadtrum Standardizes on Cadence Design Flow and Achieves One-Pass Silicon Realization for Its First 40nm Product

As one of the biggest Chinese fabless companies, Spreadtrum has been seeking greater predictability and efficiencies that will lead to a shorter time to market. By adopting Cadence-centric Silicon Realization EDA solutions, Spreadtrum gained the advantages of time to market.

“Time to market, power consumption, performance and cost efficiency are some of our major concerns at Spreadtrum as we compete in the highly competitive mobile communications market,” said Leo Li, chairman and chief executive officer at Spreadtrum. “We needed an EDA company that shares our vision and commitment to make it possible to create and deliver differentiated system-on-chip solutions. Cadence and its Silicon Realization products were the clear choice for us. This 40-nanometer chip’s one-pass success demonstrated our ability to deliver cutting-edge technology to the 3G communications industry and showcased the capability of our world-class design team with an effective and high-quality development process.”

The Cadence-centric Silicon Realization EDA tools Spreadtrum adopted include Encounter® Digital Implementation System, RTL Compiler, Conformal® Low Power, Incisive® Enterprise Simulator, Encounter® Test, Encounter® Timing System, Virtuoso® Custom Design, Multi-mode Simulation, QRC Extraction, Encounter Power System and design-for-manufacturing technologies.

“Cadence provides a recognized advantage in productivity and profitability for mobile communication device providers with our unique Silicon Realization offering,” said Charlie Huang, senior vice president and chief strategy officer at Cadence. “We are gratified that Spreadtrum—one of the leading fabless houses in the 2G/3G communication industry—standardized on the Cadence flow and has already seen early success.”