Silicon Hive Utilizes Cadence Palladium III Solution for Highest Quality IP for Multi-Core Multi-Million Gate Designs

Both companies cooperated on the integration of Palladium transaction-based acceleration (TBA) technology into Silicon Hive’s development flow. TBA allowed the design team to fully validate its RTL IP by running the complete video decoding software on the Palladium system including external system interaction.



Transaction-based acceleration (TBA) helps design and verification teams reduce their verification time by providing new infrastructure and guidelines to support a reusable accelerated verification environment running at close to emulation speed. Silicon Hive estimated the execution speed of Palladium III to be up to100 frames of H.264 full HD resolution video per 30 minutes, and was able to connect it via TBA to its system simulation environment executing control software tasks over standard bus protocols.



“On top of the acceleration speed we achieved, a major advantage of Palladium III is its full observability of our multi-core hardware, which allows short iteration cycles in co-debugging hardware and application software,” said Dr. Jeroen Leijten, CTO at Silicon Hive. “In our cooperation with Cadence, we explored options to extend Silicon Hive's power estimation flow with information provided by the Palladium System. This will allow more comprehensive analysis and reduction of the power consumed by complex software applications executed on our HiveGo hardware.”



“Emerging companies live or die based on the success of their products,” said Ran Avinun, marketing group director of system design and verification at Cadence. “Palladium III transaction-based acceleration success at Silicon Hive is another example of our ability to help customers accelerate hardware/software verification for critical projects.”