Shrinking Chip Geometry for Maximum Returns

Introduction
As semiconductor fabrication technologies continue to advance, the most advanced independent foundries are able to support processes ranging from mature geometries such as 0.18µm to cutting-edge nodes such as 28nm. Newer, smaller geometries are understood to carry higher NRE and per-wafer costs, while the larger number of dice per wafer results in a favourable unit price after production ramp-up. Other factors must also be considered, including the cost and availability of suitable IP blocks, and the costs to acquire necessary knowledge and to update the company infrastructure to work at the most advanced nodes. Non-engineering factors such as short-term and strategic corporate objectives can also have an important influence on node selection.


Competing Approaches
The two specialist chip companies described in this article produce relatively high volumes of ICs, and the devices are divided approximately equally between analogue and digital features.

Company A saw 0.18µm as the optimum technology for its custom SoC. Typically, fabrication at this node is done on 8-inch (200mm) wafers. By targeting this node, the company avoided the time and cost to acquire knowledge and IP at finer geometries. There is some sound reasoning behind this decision; miniaturising analogue circuitry for very small process geometries delivers a relatively low saving in terms of die area. Company A’s view that 0.18µm can deliver a strong combination of dense digital circuitry and competitive analogue circuitry is reasonable.

Company B chose 65nm for its competing chip design. The resulting cost for a 12-inch (300mm) wafer was a little over five times that for company A’s 8-inch wafers. This translates into a price per mm2 about two times greater. However, since the 65nm chip was less than half the size of the 0.18µm design, the smaller geometry yields a small advantage. This is diminished, however, when taking into account the higher costs for mask sets and any ROM code changes at 65nm.

Ultimately, the two companies have achieved broadly similar cost per chip. Arguably, company A has realised its product for a lower initial financial commitment. However, company B’s investment in expertise and infrastructure at 65nm, which should continue to deliver benefits in future product generations, may prove to be a more beneficial strategy in the longer term.

Node Selection Guidelines
In the example discussed, the 0.18µm process was able to achieve a competitive unit price. The design contained a relatively high proportion of RF and analogue circuitry, and the digital circuitry was already well defined in relation to mature governing standards.

In other applications - particularly for emerging generations of smart products requiring intensive digital functionality integrated on the chip - a more advanced node may present a better option. On the other hand, it is important to consider the size of the target market, bearing in mind that smaller process geometries require progressively higher production volumes to offset the increased NRE and wafer costs.

All of these factors must be considered, and a decision taken, before the design can move forward, since the target node has an important influence on the choice of foundry. It is vital to select a wafer foundry partner offering the best price and support at the chosen node. Node selection must also be determined before any third-party IP is sourced so that the detailed chip design can begin.

Analogue or Digital Miniaturisation
The relative proportions of analogue and RF to the digital circuitry included in a SoC design have an important bearing on the economics of migrating to a smaller process node.

Since digital feature size reduces according to a square function, halving the process geometry yields features occupying one quarter of the previous die area. On the other hand, the same change in design rule will yield savings between zero and 50% for analogue circuit features. Hence, systems containing a significant quantity of analogue or RF circuitry will deliver a relatively small return in exchange for the higher investment and cost-per-mm2 that are incurred at progressively smaller process nodes.

IP Assessment
For many projects at mature nodes, most or all of the required IP blocks, such as cell libraries, I/Os and memories as well as more complex blocks such as PCI Express or USB functions, can be provided by the foundry at no extra charge. However, for more advanced nodes, third-party IP is often needed.

Larger semiconductor companies may develop their own functions as required, but today IP is more typically bought on the open market. If the functions needed are not available for the desired node, or if the costs are considered excessive, a less advanced node may be a more viable choice. As a guide, third-party Flash IP blocks for leading-edge nodes may cost in the region of $10-30k, while more complex blocks such as PCI Express functions, USB, or advanced memories such as DDR3 are typically priced from $100k to as high as $700k.

Selecting IP may not be straightforward, particularly for more advanced nodes. It is worth pointing out that the most advanced nodes, generally, do not benefit from a full portfolio of supporting IP; some custom IP development may be necessary.

NRE and Wafer Pricing Assessment
The results achieved by the two example chip design projects discussed earlier highlight how differing NRE costs and per-wafer prices influence the final unit cost for each die. Table 1 compares the combined costs of NRE and mask set, as well as wafer prices, for currently active process nodes from 0.18µm to 28nm. It is also worth noting that today’s most advanced nodes deliver greater cost benefits at high volumes significantly over 100 million units per year. An accurate guide is to consider the most advanced nodes only for projects where very high production volumes are projected and the design contains a large quantity of digital circuitry. For lower volume designs, or where a significant proportion of analogue circuitry is included, a more mature process may result in the lowest cost per unit.

Process node Wafer size Relative NRE + mask cost Relative wafer price
0.18µm 200mm 1x 1x
0.13µm 200mm 2x 1.5x
90nm 200/300mm 4x 2x
65nm 300mm 8x 3x
40nm 300mm 15-20x 4.5x
28nm 300mm 25-30x 6x

Table 1. Comparison of NRE/mask costs and wafer price for foundry nodes.

Projected Production Volume
The relatively easy accessibility of today’s more mature nodes, such as 0.18µm and 0.13µm, can allow fabless chip companies to deliver commercially viable custom chip solutions for lower-volume sectors, such as some industrial and medical markets. Here, the high initial costs of the more advanced nodes can demand production volumes well beyond the total available market in order to become economically viable.

Negotiable Factors
Before committing to a node, serious dialogue with potential foundry partners is essential. Better pricing may be available if the foundry is particularly interested in the project: high projected production volumes may allow the foundry to offer one of its more advance nodes at a competitive rate; alternatively, foundries may offer lower rates to long-term, high volume customers. For this reason, foundries tend to favour larger customers. An alternative is to go through a broker or consultant that can provide the benefit of established relationships with the major foundries.

In practice, working through a consulting partner can overcome many of the potential pitfalls that can be encountered when working with an offshore foundry, across cultures and geographical boundaries. With experience, some fabless chip companies may feel that one particular foundry is easier or more reliable to work with than some others; in fact, most foundries are equally reliable provided a mutual understanding can be established.

It is also important to bear in mind that the chosen process will continue to mature throughout the duration of the project, resulting in improvements in aspects such as IP availability as well as process yield. By the time the project reaches the production ramp-up stage, most foundries can be expected to achieve acceptable yields at the target node. In addition foundries will continue to develop new process technologies, such that the most advanced process available at the beginning of the project will no longer be the most advanced by the time full production is reached.

Conclusion
There is a case for targeting the most advanced node that is practicable at the time. On the other hand, a profitable result may be achievable at a more mature node. The decision is essentially commercially driven, based on the projected sales volume and target selling price. Factors including the quantity of funding available to start the project, the level of expertise in the candidate nodes, and the corporate roadmap for future generations of the product also have a critical impact on node selection.

Arguably, today’s mature sub-micron nodes allow fabless chip companies to realise new designs at a relatively low initial cost. On the other hand, choosing a more advanced node may deliver better results in the longer term, for those companies able to bear the higher up-front costs.