New PCI Express Root Complex Lite Solution Uses The LatticeECP3 FPGA Family

Lattice's PCI Express RC Lite solution is supported by Lattice’s IPexpress™ FPGA design tool module. Included as a standard feature in the Lattice Diamond™ design environment, the IPexpress module significantly reduces design time by allowing IP parameterization and timing analysis on the designer’s desktop. This allows users to customize Lattice's extensive library of IP functions for their unique applications, integrate them with their proprietary FPGA logic designs and evaluate the overall device operation via simulation and timing analysis prior to making any IP purchase commitments.

“An FPGA-based PCI Express RC Lite solution provides system designers with a flexible way to support intelligent bridging functions between today's high-performance ASSPs that support only the serial PCI Express host interface and legacy CPU parallel host interfaces. Users may choose to maintain support for legacy CPUs due to legacy code compatibility, and/or because the CPU has been qualified for certain markets, such as Military, Satellite or Industrial,” said Lalit Merani, Lattice Senior Product Marketing Manager.

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The PCI Express RC Lite IP core provides a x1 or x4 root complex solution from the electrical SERDES interface, physical layer, data link layer and a minimum transaction layer in the PCI express protocol stack. The PCI Express 1.1 x1 RC Lite IP core requires approximately 4500 FPGA look-up tables (LUTs) in 16-bit mode. The PCI Express 1.1 x4 RC Lite IP core requires approximately 10,500 FPGA LUTs in 64-bit mode.