/> National’s ML571-1982CLK reference design clock module plugs into the Xilinx ML571 development board to create a complete video reference design for triple-rate (3G/HD/SD) SDI applications. The ML571-1982CLK delivers the industry’s lowest clock output jitter of 40 ps peak-to-peak (at 148.5 MHz) to drive the Virtex-5 LXT FPGA’s integrated SerDes without the need for additional clock cleaning circuitry.

The reference design module features National’s highly integrated LMH1982 multi-rate video clock generator and LMH1981 sync separator devices. The LMH1982 produces a top of frame (TOF) timing pulse output and can generate two simultaneous standard-definition (SD) and high-definition (HD) output clocks genlocked to the recovered H and V syncs from either a Xilinx Virtex-5 LXT FPGA, or from the outputs of a LMH1981 sync separator.

The LMH1982 supports NTSC/525i, PAL/625i, 525p, 625p, 720p, 1080i and 1080p video timing. This 5 mm by 5 mm device requires only one external 27 MHz voltage-controlled crystal oscillator (VCXO), which significantly reduces board space and design complexity. In the event of a loss of reference, the LMH1982 can be configured to default to either free run or holdover operation. In addition, the LMH1982 features a programmable charge pump current-control register for dynamic control of phase-lock loop (PLL) bandwidth. This allows a wide-loop bandwidth to be programmed for faster PLL lock time or a narrow-loop bandwidth for maximum input attenuation.