Faster Clock Speed or More Parallelization? That is the Question!

LTE represents a greater than 50x increase in maximum user data from its 3G predecessor, W-CDMA, in its maximum configuration (of course, we all know that theoretical maximum data rates are never achieved, nevertheless, the point is still valid). Due to the real time nature of baseband data, this huge increase in data must still be processed in real time. So the only way for a baseband system to compensate for the increased throughput is to significantly decrease latency.

For this reason, the Time Transmission Interval for LTE is a mere 1ms, compared to 10ms for W-CDMA. TTI is essentially the length of time to transmit a block of data. Bottom line, the need to process and transmit more than an order-of-magnitude increase in data is creating significant performance demands on cellular baseband processors. This is also true of the next generation WiFi standard, 802.11ac, which promises 1Gbps of data.

Typically, performance increases in both the user and control plane come from increasing the clock frequency of the processor. Of course, this is counter-productive to power consumption, which is why this is generally not favored in the first place. Hence, another alternative is to go multi-core, which is a common means of distributing the processing load to achieve higher performance without having to greatly increase the clock frequency. While this does increase static power consumption due to the increase in transistor count, it is less significant than the increased dynamic power consumption associated with doubling the clock frequency. Multi-core also has the downside of the potential additional licensing and royalties of the 2nd core, as well as the increased manufacturing cost from the greater die size.

Fortunately, these are not the only possibilities. Another possibility is to use hardware multi-threading, which can made a processor core look like two cores, each of which could run an independent OS or RTOS. In this case, the processing load is distributed across what appears to the RTOS to be two cores. In the MIPS32 34K core, these are known as VPEs, or Virtual Processing Elements. With a multi-threaded core, the increase in die size is relatively small and there is no need to pay a license fee or royalties for a second core. Furthermore, latency can be significantly decreased since threads can be parked and revived with a zero overhead context switch, hence achieving the two main technical requirements. One of our baseband customers simulated its multi-mode modem and found that with MIPS multi-threading, processor stalls were reduced by over 20%! All of this leads to an improved mobile device user experience, as responsiveness is greatly increased.

The biggest downside to usage of hardware multi-threading is some increase of software complexity, and porting of legacy software. Software which runs single-threaded must be re-architected in order to fully exploit the benefits of multi-threading. While this is not a complete re-write, it can be substantial. Of course, the same is also true of multi-core, so software which supports multi-threading is an inevitability. So regardless, this needs to be done. The exact level of effort depends largely on how well the code is structured (the more modular, the better), written, and documented. For a multi-mode modem, the code can be partitioned in a few different ways to exploit multi-threading while minimizing the porting cost. Stay tuned for my next post to learn more!

So the answer to the question above is, of course, it depends. It depends on the application requirements, particularly the power threshold. But for mobile baseband processors, clearly multi-threading provides a solution that increases performance significantly in a much more power friendly manner than doubling the clock speed or going multi-core.