Mentor Graphics awarded Product of the Year Award 2016
Mentor Graphics Corporation has announced that its Tessent DefectSim product was awarded 2016 Product of the Year by Electronic Products magazine. This award is presented for a product launched in 2016 that represents innovative design and advancement in technology, as determined by the editors of the publication.
The Tessent DefectSim product measures the defect coverage of any test applied to an analogue or mixed-signal circuit. This tool enables a designer to improve the quality of analogue and mixed-signal circuits during Integrated Circuit (IC) design by guiding Design-For-Test (DFT) and the selection of more effective manufacturing tests. It also enables test engineers to reduce test costs by showing which tests do not increase coverage and whether simpler or faster tests could achieve higher coverage. The tool satisfies the growing defect-coverage measurement requirement for automotive ICs set by Tier1 automotive suppliers in accordance with the ISO 26262 automotive functional safety standard.
The Tessent DefectSim tool works with Mentor’s Eldo and Questa ADMS simulators to measure the likelihood-weighted percentage of opens, shorts, extreme variations, and user-defined defect or fault models that can be detected within a layout-extracted or schematic netlist. The Tessent DefectSim product combines many techniques, described in our peer-reviewed papers, to reduce total simulation time by many orders of magnitude compared to simulation of every potential defect in a flat layout-extracted netlist, without reducing simulation accuracy or the choice of tests. “We are gratified to receive this industry recognition for an analysis tool that has taken many years to develop, and is the only general-purpose, analog fault simulator available commercially,” said Stephen Sunter, Engineering Director for mixed-signal DFT at Mentor Graphics.
“We thank the many customers who evaluated the Tessent DefectSim tool and provided so much constructive feedback to help ensure that their AMS designers will have the fault simulation capability that digital designers have had for 30 years and which has facilitated tremendous advances in automation for digital DFT and test generation.”