Magma Talus-Based RTL-to-GDSII Reference Flow for MIPS Processor IP Delivers Repeatable Results, Speeds Deployment

Based on Talus 1.1, the latest release of Magma’s IC implementation system, the flow leverages the Talus Design synthesis tool’s enhanced clock tree synthesis and the Talus COre™ technology which performs timing optimization concurrently during routing. These advanced capabilities allow designers to achieve timing closure faster. In addition, synthesis results using these reference flows for Talus 1.1 show performance improvements of as much as seven percent when compared to results using Talus 1.0.

“With today’s tight time-to-market requirements, design teams don’t have time to set up and validate design flows,” said Art Swift, vice president of marketing, MIPS Technologies. “We’re seeing increasing traction in the market for MIPS’ highest performance processor cores. Using the Talus-based reference flow with these cores, MIPS’ and Magma’s mutual customers can accelerate design and delivery of innovative SoC devices to meet the ever increasing challenges of today’s advanced applications for digital home, networking, mobile devices and beyond.”

“Successful SoC implementation is dependent on having reliable IP and a proven flow,” said Premal Buch, general manager of Magma’s Design Implementation Business Unit. “By incorporating advanced capabilities into Talus 1.1, such as early clock tree modeling, advanced crosstalk optimization, concurrent optimization during routing and providing reference flows, Magma is equipping designers with the technology they need for silicon success.”