Magma Announces SiliconSmart ACE -- New Standard in IP Characterization for 28 nm and Below

Magma Design Automation today announced SiliconSmart ACE, a next-generation intellectual property characterization and modeling tool and the latest addition to the industry-standard SiliconSmart product line. By leveraging new Accelerated Circuit Engine (ACE) technology and embedding Magma's ultra-fast FineSim(TM) SPICE simulator, the fully automated SiliconSmart ACE flow delivers more accurate models and faster turnaround time than other tools, setting a new standard in IP characterization and modeling for designs targeted at 28-nanometer (nm) and smaller process nodes.

SiliconSmart ACE is an advanced characterization system that automatically performs static structural analysis on transistor-level netlists of simple standard cells and very complex custom cells or macros. It uses the results of this analysis to set up complete characterization constraints and then leverages the foundry-certified, highly accurate and ultra-fast FineSim SPICE simulator to increase the overall throughput of timing, power, noise and statistical static timing analysis (SSTA) model generation. SiliconSmart ACE not only offers faster characterization capabilities than other tools, it supports all industry-standard model formats and includes a closed-loop model validation flow that allows users to seamlessly launch third-party tools within the Magma system to verify the generated models.

With SiliconSmart ACE, IP developers no longer need in-depth knowledge of a circuit's electrical operation to properly set up a characterization run. Delayed delivery of critical models for system-on-a-chip (SoC) sign-off or errors in modeling can be virtually eliminated, said Anirudh Devgan, general manager of Magma's Custom Design Business Unit. The breakthrough technology in SiliconSmart ACE extracts functionality, identifies all electrical arcs, and optimizes the complete characterization methodology for efficiency and accuracy, significantly reducing the time and effort to model any IP component.