Learn to design CPLDs and FPGAs “@MachX02 Speed” with Lattice Semiconductor on 21 November 2012

Adrian Elms, Business Development Director at MSC Gleichmann said, “Although primarily targeted at design engineers, this seminar will be of value to R&D managers, decision makers and other engineers who want to understand how this technology can accelerate system development. It also provides delegates with an opportunity to meet and network with representatives from Lattice.” He also commented, “These events are incredibly popular, so we have to allocate places on a first come, first served basis.”

The seminar runs from 10am to 4pm and costs £49.99, which includes a buffet lunch, a USB memory stick containing all the presentation material, user guides and reference designs plus a hardware development kit.