Lattice Announces Low Cost Programmable SPI-4.2 Solution

Lattice's SPI-4.2 solution is supported by Lattice’s IPexpress™ FPGA design tool module. Included as a standard feature in the Lattice Diamond™ design tool suite, the IPexpress module significantly reduces design time by allowing IP parameterization and timing analysis on the designer’s desktop. This allows users to customize Lattice's extensive library of IP functions for their unique applications, integrate them with their proprietary FPGA logic designs and evaluate the overall device operation via simulation and timing analysis prior to making any IP purchase commitments.

“An FPGA-based SPI-4.2 solution provides system designers with a flexible way to support intelligent bridging functions interfacing with today's high-performance communications ASSPs, including network processors, traffic managers, MACs or framers,” said Shakeel Peera, Director of Marketing for High Density Solutions. “Until now, designers could implement full rate SPI-4.2 bridges supporting complex packet flow and traffic management policies in most cases only on premium FPGA devices. The LatticeECP3 FPGA changes the game by providing designers with a low-cost, low-power SPI4.2 solution.”

The new SPI-4.2 soft IP core requires about 4000 FPGA look-up tables (LUTs) in 128-bit mode for a full 256-channel static mode core. It therefore can be implemented along with other user logic in all LatticeECP3 family members, from the LatticeECP3-17 device through the largest member of the family, the LatticeECP3-150 device. The SPI-4.2 core operates at interface speeds of up to 11.2Gbps, while fulfilling all requirements of the SPI-4.2 interface protocol, including support for up to 256 logic channels, calendars, transmit and receive status, programmable burst size and DIP4 error checking.