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Lattice and Epson Toyocom Provide Low-Cost, High Frequency Differential Reference Clock Solution

12th October 2009

Lattice Semiconductor Corporation

ES Admin

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Lattice Semiconductor and Epson Toyocom Corporation today announced a low-cost reference clock solution for SERDES applications. By utilizing Lattice's ispClock 5400D device and the appropriate SG-710ECK CMOS oscillator from Epson Toyocom, a designer now has a low cost reference clock for SERDES applications such as XAUI or SDI Video. With this solution, SERDES-based designs no longer will require an expensive LVDS or LVPECL high frequency oscillator.

XAUI, SDI Video and other SERDES applications can now utilize the ultra low-noise, programmable differential output of the Lattice ispClock device, driven by Epson Toyocom's low-cost CMOS oscillator. This solution is a compelling alternative to traditional, more expensive high frequency differential clock sources. An application note provides detailed information: Download the ispClock/Epson Application Note

SERDES (SERializer/DESerializer) applications typically use costly differential interface oscillators with frequencies greater than 150MHz to meet stringent jitter specifications. Lattice's ispCLOCK5400D device has a low phase noise on-chip PLL that generates these higher clock frequencies. This high frequency is generated by multiplying an Epson Toyocom low-cost, lower frequency CMOS oscillator. The ispCLOCK5400D device accepts the oscillator's CMOS input. This input is then multiplied up to the appropriate frequency for the SERDES reference clock rate. The solution is available for popular SERDES reference clock frequencies such as 156.25 MHz, 270 MHz and 312.50 MHz. The programmable output interface of the ispClock5400D device can drive multiple differential interface requirements such as LVDS or LVPECL. For example, with this reference clock the LaticeECP3™ FPGA implementing XAUI and SDI Video functions met jitter requirements across the industrial temperature range. ispCLOCK5400D evaluation boards are available for customers to examine this solution.

Lattice and Epson Toyocom are excited to offer this joint solution, said Chris Fanning, Corporate Vice President and General Manager, Low Density and Mixed Signal Solutions. Customers will reduce their solution cost for reference clocks and have the added value of clock distribution capability. In addition, customers may also use the solution as a standard across a wide variety of applications using the programmable differential clock and programmable skew feature of the ispClock54000D device.