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LATTICE MachXO2 PLD FAMILY: Offers up to 30% Lower Cost and Over 100X Power Reduction

14th December 2010

Avnet Abacus

ES Admin

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Datasheet

The new MachXO2 PLD family from Lattice offers designers of low-density PLDs an unprecedented mix of low cost, low power and high system integration in a single device. Built on a low power 65-nm process featuring embedded Flash technology, the MachXO2 family delivers a 3X increase in logic density, a 10X increase in embedded memory, more than a 100X reduction in static power and up to 30% lower cost compared to the MachXO™ PLD family. In addition, several popular functions used in low-density PLD applications, such as User Flash Memory (UFM), I2C, SPI and timer/counter, have been hardened into the MachXO2 devices, providing designers a “Do-it-All-PLD” for high volume, cost sensitive designs

Three Product Options For Maximum Flexibility

1. The MachXO2 family offers three options for maximum flexibility. MachXO2 ZE devices range from 256 to 7K look-up tables (LUTs), operate off a nominal 1.2V power supply, and support system performance up to 60MHz. With power specified as low as 19uW and packages as small as 2.5mmx2.5mm, the MachXO2 ZE devices are optimized for cost-sensitive, low power consumer design applications such as smart phones, GPS devices and PDAs.

2. MachXO2 HC devices range from 256 to 7K LUTs, operate off a nominal 3.3V or 2.5V power supply, and support system performance up to 150MHz. Offering up to 335 user I/O and a robust design solution (instant-on, non-volatile, input hysteresis and single-chip), these devices are ideal for control applications in end markets such as telecommunications infrastructure, computing, industrial and medical equipment.

3. MachXO2 HE devices range from 2K to 7K LUTs, operate off a nominal 1.2V power supply and support system performance up to 150MHz. These devices are optimized for power sensitive system applications.