Analysis

Inphi Announces Next Generation 100 Gigabit Ethernet CMOS SerDes Architecture

11th April 2011
ES Admin
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Inphi Corporation announced a new 100 GbE CMOS SerDes architecture, called iPHY, designed to enable the development of next generation low power and high port density 100 Gigabit Ethernet (100 GbE) solutions to address bandwidth bottlenecks in next generation data center and communications infrastructures.
“Inphi continues to innovate. Our iPHY CMOS architecture is specifically designed to enable the development of next generation low power and small form factor 100 GbE transceivers,” said Young Sohn, President and CEO, Inphi. “Together, working closely with leading OEMs and ecosystem partners, we can deliver more than 2X reduction in power and size, and 10X increase in port density for 100 GbE transceivers versus existing solutions based upon silicon-germanium technology. We believe this helps accelerate the mass transition from 10 GbE to 100 GbE in data center and communications infrastructures.”

Cost-effective, energy-efficient 100 GbE links are expected to become important tools for data center and service provider networks, which are seeking to address the demand for increased/greater bandwidth. The evolution of the 100 GbE transceivers necessary to support this growth is expected to follow a path similar to that of the earlier Gigabit Ethernet and 10 GbE technologies, which evolved from power-hungry, large form factor, and niche transceivers to low power, small form factor, and high volume products. There are two critical steps on this path:

First, migrate the 100 GbE transceiver’s high-speed SerDes from its present implementation in exotic silicon-germanium (SiGe) technology to low power CMOS designs that can be economically fabricated using mainstream commercial CMOS processes.

Second, introduce innovative architectures that significantly reduce the power consumption and size of the transceivers.

The Inphi iPHY architecture is designed to address these steps and offer comprehensive solutions for physical layer integrated circuits (ICs) inside the transceiver module and on the line card to enable next generation 100 GbE systems to achieve more than 2X reduction in transceiver power consumption and 10X increase in port density.

Inphi embarked on its iPHY architecture in 2009, and is working closely with leading networking OEMs and ecosystem partners to develop the 100 GbE CMOS SerDes technology. In addition, Inphi has been actively driving the development of next generation low power and high port density 100 GbE standards at the IEEE and the Optical Internetworking Forum (OIF) meetings.

“The demand for network bandwidth is experiencing high growth, partially driven by the increase of mobile devices and wireless connectivity and users seeking faster access to high-performance applications, such as high-definition video and multimedia content,” said Daryl Inniss, Ovum’s Component VP and Practice Leader. “Ovum estimates demand for 100 GbE transceivers to grow at a high compounded annual growth rate of over 100% from 2010 to 2013, well above the industry average of 14%, because these transceivers are an emerging cost-effective solution supporting the bandwidth growth.”

The iPHY architecture is Inphi’s latest step in expanding its 100G offerings to address the bandwidth bottlenecks in data centers and communications infrastructures. Inphi anticipates sampling its first 100 GbE CMOS SerDes products in the second half of 2011.

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